Reducing the number of pins required by an integrated circuit is normally one important factor in reducing overall packaged integrated circuit device size and cost. Additionally, integrated circuit devices with smaller numbers of pins typically assist in reducing the design complexity at the higher levels of the system application. At the same time, any reduction in the number of pins cannot unduly limit the input/output capability of the integrated circuit nor unreasonably constrain the range of operations available to the end user. This situation is particularly true in regard to integrated circuit devices that support multiple modes, such as digital audio devices which can be utilized in either pulse code modulation (PCM) or Direct Stream Digital (DSD) applications and thereby support different application options in a single package.
A pulse code modulated (PCM) audio system typically utilizes three clocks and a single stream of PCM—encoded serial audio data (SDATA). Specifically, an external master clock (EMCK) signal controls the overall timing of the processing operations, a serial or bit clock (SCLK) signal times the transfer of the individual bits of serial PCM audio data, and a left-right clock (LRCK) signal differentiates between left and right stereo data samples in the PCM data stream. On the other hand, the Direct Stream Digital (DSD) protocol, used to record audio under the Sony/Philips Super Audio Compact Disk (SACD) standard, is based on two channels of one-bit audio data (DSDA and DSDB) and a single serial clock (DSD—CLK) signal. The DSD protocol also utilizes the external master clock EMCK. Therefore, in order to accommodate both modes in a single flexible and efficient integrated circuit device, an input/output scheme must be developed which addresses the differences between the DSD and PCM protocols with a minimum number of pins.
One current approach to providing the required input/output capability in DSD—PCM multiple-mode devices utilizes two independent sets of pins, one set for exchanging DSD protocol data and clock signals, and another set for exchanging PCM data and clock signals. This technique, however, is contrary to the goal of reducing the number of pins on the packaged device and/or overall package size. Another conventional approach is to share some pins for both the DSD and PCM modes, and dedicating other pins for supporting only one mode or the other. For example, one or more of the pins required for exchanging PCM mode clock signals might be also used for exchanging one channel of data in the DSD mode. However, this scheme normally requires additional internal and external control circuitry and /or one or more mode control pins for configuring the data and clock pins to support the selected operating mode.
Consequently, new techniques are required for supporting multiple-mode integrated circuits with a minimum number of pins. In particular, such techniques should not require the dedication of one or more available pins for mode configuration purposes nor require substantial additional control circuitry.